We study the structure of SiC/SiO2 interface defects and the effects of negative bias temperature stress (NBTS) in lateral 4H silicon carbide (SiC) PMOSFETs. Our devices have 90 nm thick SiO2 gate oxides thermally grown in N2O ambient at 1280°C on n-type SiC. We investigate virgin (unstressed) and stressed devices using two different techniques: (i) for electrical characterization, we use the direct-current current-voltage (DCIV) technique  which measures a recombination current via interface defects and charge pumping (CP) which measures the number of interface defects within a certain range of the SiC band gap; (ii) to study the structure of the defects, we use electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) . The elevated temperature during NBTS is provided by in-situ heated test structures. This is the first EDMR study of p-doped SiC MOSFETs and the first negative bias temperature instability (NBTI) study of SiC MOSFETs using in-situ (on-chip) heating during stress.