Interface traps in silicon carbide MOSFETs

C. J. Cochrane, Patrick M. Lenahan, A. J. Lelis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In "classical" MOS technology, reliability and performance limiting defects are, as a rule, precisely at the semiconductor/ insulator interface and very near that interface on the dielectric side. In the Si/SiO 2 system, the dominating defects have typically been silicon dangling bond defects. During the last few years there has been a great deal of interest in "new materials" based MOS technologies. In these new devices, the physical location and chemical nature of performance limiting defects may be very different from the Si/SiO 2 case. In this study we show that "interface traps" in 4H SiC MOSFETs may be very strongly influenced by the quality of the SiC substrate, with defects in that substrate present at densities which can be comparable to or in excess of the defect densities precisely at the semiconductor/ dielectric interface. Using DCIV and magnetic resonance measurements, we explore the physical location and chemical nature of these performance limiting defects in variously processed SiC MOSFETs.

Original languageEnglish (US)
Title of host publication2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008
Pages68-71
Number of pages4
DOIs
StatePublished - Dec 1 2008
Event2008 IEEE International Integrated Reliability Workshop, IRW 2008 - South Lake Tahoe, CA, United States
Duration: Oct 12 2008Oct 16 2008

Other

Other2008 IEEE International Integrated Reliability Workshop, IRW 2008
CountryUnited States
CitySouth Lake Tahoe, CA
Period10/12/0810/16/08

Fingerprint

Silicon carbide
Defects
Magnetic resonance measurement
Semiconductor materials
Dangling bonds
Defect density
Silicon
Substrates
silicon carbide

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

Cite this

Cochrane, C. J., Lenahan, P. M., & Lelis, A. J. (2008). Interface traps in silicon carbide MOSFETs. In 2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008 (pp. 68-71). [4796089] https://doi.org/10.1109/IRWS.2008.4796089
Cochrane, C. J. ; Lenahan, Patrick M. ; Lelis, A. J. / Interface traps in silicon carbide MOSFETs. 2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008. 2008. pp. 68-71
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Cochrane, CJ, Lenahan, PM & Lelis, AJ 2008, Interface traps in silicon carbide MOSFETs. in 2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008., 4796089, pp. 68-71, 2008 IEEE International Integrated Reliability Workshop, IRW 2008, South Lake Tahoe, CA, United States, 10/12/08. https://doi.org/10.1109/IRWS.2008.4796089

Interface traps in silicon carbide MOSFETs. / Cochrane, C. J.; Lenahan, Patrick M.; Lelis, A. J.

2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008. 2008. p. 68-71 4796089.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Cochrane CJ, Lenahan PM, Lelis AJ. Interface traps in silicon carbide MOSFETs. In 2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008. 2008. p. 68-71. 4796089 https://doi.org/10.1109/IRWS.2008.4796089