Intrinsic doping and gate hysteresis in graphene field effect devices fabricated on SiO2 substrates

P. Joshi, H. E. Romero, A. T. Neal, V. K. Toutam, S. A. Tadigadapa

Research output: Contribution to journalArticle

106 Scopus citations

Abstract

We have studied the intrinsic doping level and gate hysteresis of graphene-based field effect transistors (FETs) fabricated over Si/SiO 2 substrates. It was found that the high p-doping level of graphene in some as-prepared devices can be reversed by vacuum degassing at room temperature or above depending on the degree of hydrophobicity and/or hydration of the underlying SiO2 substrate. Charge neutrality point (CNP) hysteresis, consisting of the shift of the charge neutrality point (or Dirac peak) upon reversal of the gate voltage sweep direction, was also greatly reduced upon vacuum degassing. However, another type of hysteresis, consisting of the change in the transconductance upon reversal of the gate voltage sweep direction, persists even after long-term vacuum annealing at 200°C, when SiO2 surface-bound water is expected to be desorbed. We propose a mechanism for this transconductance hysteresis that involves water-related defects, formed during the hydration of the near-surface silanol groups in the bulk SiO2, that can act as electron traps.

Original languageEnglish (US)
Article number334214
JournalJournal of Physics Condensed Matter
Volume22
Issue number33
DOIs
StatePublished - Aug 25 2010

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics

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