Abstract
In this paper, a novel architecture for 2-D IDCT is proposed, based on the sparseness property of 2-D DCT coefficient matrix and the even and odd symmetry property of the basis vectors of the 1-D DCT transform. The proposed architecture performs 2-D IDCT directly on the 2-D DCT coefficient matrix to avoid timing and area overheads of the transposition. We derive a recursion equation from the definition of the 2-D IDCT algorithm and use it to design an efficient 2-D IDCT architecture. The proposed architecture consists of highly regular, parallel and pipelined elements which are suitable for VLSI implementation. It is shown that the proposed architecture can achieve a high throughput rate and a low hardware complexity, when compared with other DCT-based IDCT architectures. Another important aspect is that the proposed architecture can provide an efficient way to control the trade-off between visual quality of the reconstructed image and computational complexity.
Original language | English (US) |
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Pages (from-to) | 361-366 |
Number of pages | 6 |
Journal | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
State | Published - Dec 1 2004 |
Event | 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings - Austin, TX, United States Duration: Oct 13 2004 → Oct 15 2004 |
All Science Journal Classification (ASJC) codes
- Media Technology
- Signal Processing