Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motions estimation codes, we look at the influence of compiler optimizations on the memory system energy considering the overall impact of instruction and data accesses.
|Original language||English (US)|
|Number of pages||15|
|State||Published - 2001|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering