Abstract
Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.
| Original language | English (US) |
|---|---|
| Title of host publication | 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011 |
| DOIs | |
| State | Published - 2011 |
| Event | 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011 - Colorado Springs, CO, United States Duration: Jun 20 2011 → Jun 25 2011 |
Other
| Other | 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011 |
|---|---|
| Country | United States |
| City | Colorado Springs, CO |
| Period | 6/20/11 → 6/25/11 |
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All Science Journal Classification (ASJC) codes
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
Cite this
}
Invited paper : Accelerating neuromorphic vision on FPGAs. / Park, Sungho; Kestur, Srinidhi; Irick, Kevin M.; Narayanan, Vijaykrishnan.
2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011. 2011. 5981826.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Invited paper
T2 - Accelerating neuromorphic vision on FPGAs
AU - Park, Sungho
AU - Kestur, Srinidhi
AU - Irick, Kevin M.
AU - Narayanan, Vijaykrishnan
PY - 2011
Y1 - 2011
N2 - Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.
AB - Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.
UR - http://www.scopus.com/inward/record.url?scp=80054914646&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80054914646&partnerID=8YFLogxK
U2 - 10.1109/CVPRW.2011.5981826
DO - 10.1109/CVPRW.2011.5981826
M3 - Conference contribution
AN - SCOPUS:80054914646
SN - 9781457705298
BT - 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011
ER -