Invited paper: Accelerating neuromorphic vision on FPGAs

Sungho Park, Srinidhi Kestur, Kevin M. Irick, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.

Original languageEnglish (US)
Title of host publication2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011
DOIs
StatePublished - 2011
Event2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011 - Colorado Springs, CO, United States
Duration: Jun 20 2011Jun 25 2011

Other

Other2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011
CountryUnited States
CityColorado Springs, CO
Period6/20/116/25/11

Fingerprint

Field programmable gate arrays (FPGA)
Particle accelerators
Hardware
Reconfigurable hardware
Program processors
Scalability

All Science Journal Classification (ASJC) codes

  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

Cite this

Park, S., Kestur, S., Irick, K. M., & Narayanan, V. (2011). Invited paper: Accelerating neuromorphic vision on FPGAs. In 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011 [5981826] https://doi.org/10.1109/CVPRW.2011.5981826
Park, Sungho ; Kestur, Srinidhi ; Irick, Kevin M. ; Narayanan, Vijaykrishnan. / Invited paper : Accelerating neuromorphic vision on FPGAs. 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011. 2011.
@inproceedings{a1497a80bbcf49e5b750b20e156403ff,
title = "Invited paper: Accelerating neuromorphic vision on FPGAs",
abstract = "Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.",
author = "Sungho Park and Srinidhi Kestur and Irick, {Kevin M.} and Vijaykrishnan Narayanan",
year = "2011",
doi = "10.1109/CVPRW.2011.5981826",
language = "English (US)",
isbn = "9781457705298",
booktitle = "2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011",

}

Park, S, Kestur, S, Irick, KM & Narayanan, V 2011, Invited paper: Accelerating neuromorphic vision on FPGAs. in 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011., 5981826, 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011, Colorado Springs, CO, United States, 6/20/11. https://doi.org/10.1109/CVPRW.2011.5981826

Invited paper : Accelerating neuromorphic vision on FPGAs. / Park, Sungho; Kestur, Srinidhi; Irick, Kevin M.; Narayanan, Vijaykrishnan.

2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011. 2011. 5981826.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Invited paper

T2 - Accelerating neuromorphic vision on FPGAs

AU - Park, Sungho

AU - Kestur, Srinidhi

AU - Irick, Kevin M.

AU - Narayanan, Vijaykrishnan

PY - 2011

Y1 - 2011

N2 - Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.

AB - Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. In this paper, we describe a model for designing streaming hardware accelerators with run-time configurability. This model provides a generic interface for each hardware module, a modular and hierarchical structure for parallelism at multiple levels and a run-time reconfiguration framework for increased flexibility. We present case studies to accelerate sample neu-romorphic vision algorithms which are inspired by models of the mammalian visual cortex. Experimental results show speedups of several factors over comparable CPU implementations and higher performance-per-watt over relevant GPU implementations.

UR - http://www.scopus.com/inward/record.url?scp=80054914646&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80054914646&partnerID=8YFLogxK

U2 - 10.1109/CVPRW.2011.5981826

DO - 10.1109/CVPRW.2011.5981826

M3 - Conference contribution

AN - SCOPUS:80054914646

SN - 9781457705298

BT - 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011

ER -

Park S, Kestur S, Irick KM, Narayanan V. Invited paper: Accelerating neuromorphic vision on FPGAs. In 2011 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2011. 2011. 5981826 https://doi.org/10.1109/CVPRW.2011.5981826