@article{329b77996fd348db9816b6770ad4a12c,
title = "Large-Area, Single-Layer Molybdenum Disulfide Synthesized at BEOL Compatible Temperature as Cu Diffusion Barrier",
abstract = "The scaling limit of conventional Cu diffusion barriers has become the bottleneck for interconnect technology, which in turn limits the IC performance. Sub-nm diffusion barrier is urgently demanded to maintain the interconnect resistivity for ultra-scaled Cu interconnects. However, with this thickness, the blocking capabilities of conventional Cu diffusion barriers are lost. In this letter, sub-nm Cu diffusion barrier is realized by single-layer molybdenum disulfide (MoS2) grown at 400 °C using metal-organic chemical vapor deposition. MoS2 is directly grown on dielectrics without transfer processes and the continuous coverage in a large area (>1 cm2) is achieved. Its resistance to Cu diffusion is investigated by time-dependent dielectric breakdown (TDDB) measurements. Our results indicate that the MoS2 barrier can efficiently suppress Cu diffusion and enhance dielectric lifetime significantly. Although a few challenges, including Cu adhesion to the MoS2 surface and integration with the Damascene structure, have to be assessed before introducing this novel material to the back-end-of-line technology, our work lays the groundwork for further investigation.",
author = "Lo, {Chun Li} and Kehao Zhang and {Scott Smith}, Ryan and Ketan Shah and Robinson, {Joshua A.} and Zhihong Chen",
note = "Funding Information: This work was supported in part by the Semiconductor Research Corporation (Task2658.001), NSF, under Grant CCF-1619062 and in part by the Center for Low Energy Systems Technology, one of six centers of STARnet, a Semiconductor Research Corporation program through MARCO and DARPA. The work of K. Zhang and J. A. Robinson was supported by the Center for Atomically Thin Multifunctional Coatings through NSF under Contract IIP 1540018 Funding Information: Manuscript received February 28, 2018; revised April 7, 2018; accepted April 9, 2018. Date of publication April 16, 2018; date of current version May 22, 2018. This work was supported in part by the Semiconductor Research Corporation (Task2658.001), NSF, under Grant CCF-1619062 and in part by the Center for Low Energy Systems Technology, one of six centers of STARnet, a Semiconductor Research Corporation program through MARCO and DARPA. The work of K. Zhang and J. A. Robinson was supported by the Center for Atomically Thin Multifunctional Coatings through NSF under Contract IIP 1540018. The review of this letter was arranged by Editor A. Naeemi. (Corresponding author: Zhihong Chen.) C.-L. Lo and Z. Chen are with the School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 USA (e-mail: zhchen@purdue.edu). Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",
year = "2018",
month = jun,
doi = "10.1109/LED.2018.2827061",
language = "English (US)",
volume = "39",
pages = "873--876",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",
}