Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller

Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Computer hardware is increasingly shared by distrusting parties in platforms such as commercial clouds and web servers. Though hardware sharing is critical for performance and efficiency, this sharing creates timing-channel vulnerabilities in hardware components such as memory controllers and shared memory. Past work on timing-channel protection for memory controllers assumes all parties are mutually distrusting and require timing-channel protection. This assumption limits the capability of the memory controller to allocate resources effectively, and causes severe performance penalties. Further, the assumption that all entities are mutually distrusting is often a poor fit for the security needs of real systems. Often, some entities do not require timing-channel protection or trust others with information. We propose lattice priority scheduling (LPS), a secure memory scheduling algorithm that improves performance by more precisely meeting the target system's security requirements, expressed as a lattice policy. We evaluate LPS in a simulated 8-core microprocessor. Compared to prior solutions [34], lattice priority scheduling improves system throughput by over 30% on average and by up to 84% for some workloads.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016
PublisherIEEE Computer Society
Pages382-393
Number of pages12
ISBN (Electronic)9781467392112
DOIs
StatePublished - Apr 1 2016
Event22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016 - Barcelona, Spain
Duration: Mar 12 2016Mar 16 2016

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2016-April
ISSN (Print)1530-0897

Other

Other22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016
CountrySpain
CityBarcelona
Period3/12/163/16/16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller'. Together they form a unique fingerprint.

  • Cite this

    Ferraiuolo, A., Wang, Y., Zhang, D., Myers, A. C., & Suh, G. E. (2016). Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller. In Proceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016 (pp. 382-393). [7446080] (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 2016-April). IEEE Computer Society. https://doi.org/10.1109/HPCA.2016.7446080