Layout-aware optimization of STT MRAMs

Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

44 Citations (Scopus)

Abstract

We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (W FET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for W FET less than a critical value (∼7 times the minimum feature length), one-finger transistor yields minimum cell area. For large W FET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of W FET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, W FET can be increased with no change in the cell area. We analyze the impact of increase in W FET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing W FET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Pages1455-1458
Number of pages4
StatePublished - May 24 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: Mar 12 2012Mar 16 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
CountryGermany
CityDresden
Period3/12/123/16/12

Fingerprint

Field effect transistors
Torque
Transistors
Tunnelling magnetoresistance
Metals
Magnetic anisotropy
Electric potential

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Gupta, S. K., Park, S. P., Mojumder, N. N., & Roy, K. (2012). Layout-aware optimization of STT MRAMs. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 (pp. 1455-1458). [6176595] (Proceedings -Design, Automation and Test in Europe, DATE).
Gupta, Sumeet Kumar ; Park, Sang Phill ; Mojumder, Niladri Narayan ; Roy, Kaushik. / Layout-aware optimization of STT MRAMs. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. pp. 1455-1458 (Proceedings -Design, Automation and Test in Europe, DATE).
@inproceedings{8ccad6a9fb30480fbe09b4cc1d269cf2,
title = "Layout-aware optimization of STT MRAMs",
abstract = "We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (W FET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for W FET less than a critical value (∼7 times the minimum feature length), one-finger transistor yields minimum cell area. For large W FET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of W FET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, W FET can be increased with no change in the cell area. We analyze the impact of increase in W FET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing W FET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27{\%} improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.",
author = "Gupta, {Sumeet Kumar} and Park, {Sang Phill} and Mojumder, {Niladri Narayan} and Kaushik Roy",
year = "2012",
month = "5",
day = "24",
language = "English (US)",
isbn = "9783981080186",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
pages = "1455--1458",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012",

}

Gupta, SK, Park, SP, Mojumder, NN & Roy, K 2012, Layout-aware optimization of STT MRAMs. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012., 6176595, Proceedings -Design, Automation and Test in Europe, DATE, pp. 1455-1458, 15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012, Dresden, Germany, 3/12/12.

Layout-aware optimization of STT MRAMs. / Gupta, Sumeet Kumar; Park, Sang Phill; Mojumder, Niladri Narayan; Roy, Kaushik.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. p. 1455-1458 6176595 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Layout-aware optimization of STT MRAMs

AU - Gupta, Sumeet Kumar

AU - Park, Sang Phill

AU - Mojumder, Niladri Narayan

AU - Roy, Kaushik

PY - 2012/5/24

Y1 - 2012/5/24

N2 - We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (W FET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for W FET less than a critical value (∼7 times the minimum feature length), one-finger transistor yields minimum cell area. For large W FET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of W FET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, W FET can be increased with no change in the cell area. We analyze the impact of increase in W FET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing W FET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

AB - We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (W FET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for W FET less than a critical value (∼7 times the minimum feature length), one-finger transistor yields minimum cell area. For large W FET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of W FET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, W FET can be increased with no change in the cell area. We analyze the impact of increase in W FET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing W FET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

UR - http://www.scopus.com/inward/record.url?scp=84862106053&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862106053&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84862106053

SN - 9783981080186

T3 - Proceedings -Design, Automation and Test in Europe, DATE

SP - 1455

EP - 1458

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012

ER -

Gupta SK, Park SP, Mojumder NN, Roy K. Layout-aware optimization of STT MRAMs. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. p. 1455-1458. 6176595. (Proceedings -Design, Automation and Test in Europe, DATE).