Leakage-aware compilation for VLIW architectures

W. Zhang, Y. F. Tsai, Mahmut Kandemir, Vijaykrishnan Narayanan, Mary Jane Irwin, V. De

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.

Original languageEnglish (US)
Pages (from-to)251-260
Number of pages10
JournalIEE Proceedings: Computers and Digital Techniques
Volume152
Issue number2
DOIs
StatePublished - Mar 1 2005

Fingerprint

Very long instruction word architecture
Compilation
Leakage
Compiler
Power Consumption
Electric power utilization
Unit
Chip
Data flow analysis
Leakage Current
Limiter
Sleep
Limiters
Software Design
Signal Control
Software design
Simulation Environment
Energy
Data Flow
Threshold voltage

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

Zhang, W. ; Tsai, Y. F. ; Kandemir, Mahmut ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; De, V. / Leakage-aware compilation for VLIW architectures. In: IEE Proceedings: Computers and Digital Techniques. 2005 ; Vol. 152, No. 2. pp. 251-260.
@article{f23b419e301d42a29b50e7b420f2650c,
title = "Leakage-aware compilation for VLIW architectures",
abstract = "Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.",
author = "W. Zhang and Tsai, {Y. F.} and Mahmut Kandemir and Vijaykrishnan Narayanan and Irwin, {Mary Jane} and V. De",
year = "2005",
month = "3",
day = "1",
doi = "10.1049/ip-cdt:20045059",
language = "English (US)",
volume = "152",
pages = "251--260",
journal = "IEE Proceedings: Computers and Digital Techniques",
issn = "1350-2387",
publisher = "Institute of Electrical Engineers",
number = "2",

}

Leakage-aware compilation for VLIW architectures. / Zhang, W.; Tsai, Y. F.; Kandemir, Mahmut; Narayanan, Vijaykrishnan; Irwin, Mary Jane; De, V.

In: IEE Proceedings: Computers and Digital Techniques, Vol. 152, No. 2, 01.03.2005, p. 251-260.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Leakage-aware compilation for VLIW architectures

AU - Zhang, W.

AU - Tsai, Y. F.

AU - Kandemir, Mahmut

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

AU - De, V.

PY - 2005/3/1

Y1 - 2005/3/1

N2 - Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.

AB - Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.

UR - http://www.scopus.com/inward/record.url?scp=19344374692&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=19344374692&partnerID=8YFLogxK

U2 - 10.1049/ip-cdt:20045059

DO - 10.1049/ip-cdt:20045059

M3 - Article

VL - 152

SP - 251

EP - 260

JO - IEE Proceedings: Computers and Digital Techniques

JF - IEE Proceedings: Computers and Digital Techniques

SN - 1350-2387

IS - 2

ER -