Leakage-aware interconnect for on-chip network

Yuh Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages230-231
Number of pages2
DOIs
StatePublished - 2005
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeI
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Tsai, Y. F., Narayaynan, V., Xie, Y., & Irwin, M. J. (2005). Leakage-aware interconnect for on-chip network. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 230-231). [1395561] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. I). https://doi.org/10.1109/DATE.2005.195