Leakage control in FPGA routing fabric

Suresh Srinivasan, A. Gayasen, N. Vijaykrishnan, T. Tuan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages661-664
Number of pages4
ISBN (Print)0780387368, 9780780387362
DOIs
StatePublished - 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: Jan 18 2005Jan 21 2005

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period1/18/051/21/05

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Srinivasan, S., Gayasen, A., Vijaykrishnan, N., & Tuan, T. (2005). Leakage control in FPGA routing fabric. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 661-664). [1466246] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1120987