Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs

Prasanth Mangalagiri, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design flow that will increase the average life-time of components by ensuring uniform aging. We first study the impact of temperature and voltage variations on lifetime reliability of components. In the presence of such variations, we study the impact of aging in FPGA interconnects due to Electromigration (EM), and di-electric breakdown due to Time Dependent Dielectric Breakdown (TDDB). We also consider the performance degradation due to Hot Carrier Instability (HCI) in our design flow optimizations. The proposed reliability aware design flow techniques achieve an average of 65.8% and 75% improvement in lifetime of LUTs and interconnect wires respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Pages61-66
Number of pages6
DOIs
StatePublished - Oct 5 2009
Event2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 - Tampa, FL, United States
Duration: May 14 2009May 15 2009

Publication series

NameProceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Other

Other2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
CountryUnited States
CityTampa, FL
Period5/14/095/15/09

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Mangalagiri, P., & Narayanan, V. (2009). Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs. In Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 (pp. 61-66). [5076384] (Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009). https://doi.org/10.1109/ISVLSI.2009.42