Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms

Andrea Marongiu, Luca Benini, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is barrier instructions which are used to perform global synchronization across parallel processors. This scenario calls for a lightweight synchronization infrastructure. In this work we describe a lightweight barrier support library for a non-cache-coherent MPSoC architecture. The library is coupled with a parallelizing compiler front-end to set up a complete automated flow which, starting from a sequential code, produces the parallelized binary code that can be directly executed onto an MPSoC target (a multi-core non-cache-coherent ARM7 platform). This tool-flow has been characterized in terms of system performance and energy.

Original languageEnglish (US)
Title of host publicationCASES'07
Subtitle of host publicationProceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Pages145-149
Number of pages5
DOIs
StatePublished - Dec 1 2007
EventCASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - Salzburg, Austria
Duration: Sep 30 2007Oct 3 2007

Publication series

NameCASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

OtherCASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
CountryAustria
CitySalzburg
Period9/30/0710/3/07

Fingerprint

Synchronization
Binary codes

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Cite this

Marongiu, A., Benini, L., & Kandemir, M. (2007). Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. In CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 145-149). (CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). https://doi.org/10.1145/1289881.1289908
Marongiu, Andrea ; Benini, Luca ; Kandemir, Mahmut. / Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2007. pp. 145-149 (CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).
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Marongiu, A, Benini, L & Kandemir, M 2007, Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. in CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 145-149, CASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Salzburg, Austria, 9/30/07. https://doi.org/10.1145/1289881.1289908

Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. / Marongiu, Andrea; Benini, Luca; Kandemir, Mahmut.

CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2007. p. 145-149 (CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Marongiu A, Benini L, Kandemir M. Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. In CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2007. p. 145-149. (CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). https://doi.org/10.1145/1289881.1289908