Load elimination for low-power embedded processors

Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik

Research output: Contribution to conferencePaper

Abstract

The performance requirements of emerging embedded applications are rapidly increasing. One attractive approach to increase the performance of processors, while keeping their energy consumption low, is to utilize instruction-level parallelism. Hence, we are witnessing a significant increase in the number of superscalar embedded processors, In this paper, we present a method to reduce the energy consumption in such processors. Particularly, we will show that a) the load instructions in representative applications exhibit a large address locality, i.e., two consecutive executions of the same load instruction is very likely to access the same data, and b) the register file utilization of these applications are usually low. To take advantage of these observations, we devise a load elimination scheme, which tries to store the data values of load instructions in the register file. Our results with 11 MediaBench applications reveal that this method eliminates 20.5% of all cache accesses, resulting in 11.5% reduction in the energy consumption.

Original languageEnglish (US)
Pages282-285
Number of pages4
DOIs
StatePublished - 2005
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: Apr 17 2005Apr 19 2005

Other

Other2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period4/17/054/19/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Memik, G., Kandemir, M. T., & Mallik, A. (2005). Load elimination for low-power embedded processors. 282-285. Paper presented at 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05, Chicago, IL, United States. https://doi.org/10.1145/1057661.1057729