Locality-aware mapping and scheduling for multicores

Wei Ding, Yuanrui Zhang, Mahmut Kandemir, Jithendra Srinivas, Praveen Yedlapalli

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

This paper presents a cache hierarchy-aware code mapping and scheduling strategy for multicore architectures. Our mapping strategy determines a loop iteration-to-core mapping by taking into account application data access patterns and on-chip cache hierarchy. It employs a novel concept called 'core vectors' to obtain a mapping matrix which exploits data reuses at different layers of the cache hierarchy based on their reuse distances, with the goal of maximizing data locality at each level, while minimizing data dependences across the cores. Our scheduling strategy on the other hand determines a schedule for the iterations assigned to each core, with the goal of reducing data reuse distances across the cores for dependence-free loop nests. Our experimental evaluation shows that the proposed mapping scheme reduces miss rates at all levels of caches and application execution time significantly, and when supported by scheduling, the reduction in cache miss rates and execution time become much larger.

Original languageEnglish (US)
Title of host publicationProceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013
DOIs
StatePublished - May 6 2013
Event11th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013 - Shenzhen, China
Duration: Feb 23 2013Feb 27 2013

Publication series

NameProceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013

Other

Other11th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013
CountryChina
CityShenzhen
Period2/23/132/27/13

All Science Journal Classification (ASJC) codes

  • Applied Mathematics
  • Control and Optimization

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