Low-leakage robust SRAM cell design for sub-100nm technologies

Shengqi Yang, Wayne Wolf, Wenping Wang, Vijaykrishnan Narayanan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important issues have been separately addressed in previous SRAM designs, there exists no design that simultaneously cuts down leakage power and enhances the resistance to soft error. In this work, we have built the first such SRAM cell, by hybrid of higlw,-. gate dielectric and dynamic threshold voltage which is realized in the form of jointly biased gate and substrate transistor. The HSRAM not only makes the gate leakage negligible, but lessens the severe increase of subthreshold leakage caused by Fringing/Field Induced Barrier Lowering (FIBL) effect accompanied with the introduction of high-ft gate dielectric, and in the same time reduces the susceptibility to soft error by increasing the node capacitance. Experiments were performed in both transistor level and circuit level for this novel HSRAM using ISE8.U and HSPICE. They indicate that up to 03% reduction in total leakage is possible by using HSRAM cell, with an up to 23% increase in reliability degree and and an up to 73% reduction in bitline delay, compared to standard 6T SRAM.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages539-544
Number of pages6
StatePublished - Dec 1 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: Jan 18 2005Jan 21 2005

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period1/18/051/21/05

Fingerprint

Static random access storage
Gate dielectrics
Transistors
Threshold voltage
Capacitance
Networks (circuits)
Substrates

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Yang, S., Wolf, W., Wang, W., Narayanan, V., & Xie, Y. (2005). Low-leakage robust SRAM cell design for sub-100nm technologies. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 539-544). [1466222] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).
Yang, Shengqi ; Wolf, Wayne ; Wang, Wenping ; Narayanan, Vijaykrishnan ; Xie, Yuan. / Low-leakage robust SRAM cell design for sub-100nm technologies. Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. pp. 539-544 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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abstract = "A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important issues have been separately addressed in previous SRAM designs, there exists no design that simultaneously cuts down leakage power and enhances the resistance to soft error. In this work, we have built the first such SRAM cell, by hybrid of higlw,-. gate dielectric and dynamic threshold voltage which is realized in the form of jointly biased gate and substrate transistor. The HSRAM not only makes the gate leakage negligible, but lessens the severe increase of subthreshold leakage caused by Fringing/Field Induced Barrier Lowering (FIBL) effect accompanied with the introduction of high-ft gate dielectric, and in the same time reduces the susceptibility to soft error by increasing the node capacitance. Experiments were performed in both transistor level and circuit level for this novel HSRAM using ISE8.U and HSPICE. They indicate that up to 03{\%} reduction in total leakage is possible by using HSRAM cell, with an up to 23{\%} increase in reliability degree and and an up to 73{\%} reduction in bitline delay, compared to standard 6T SRAM.",
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Yang, S, Wolf, W, Wang, W, Narayanan, V & Xie, Y 2005, Low-leakage robust SRAM cell design for sub-100nm technologies. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466222, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 539-544, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05.

Low-leakage robust SRAM cell design for sub-100nm technologies. / Yang, Shengqi; Wolf, Wayne; Wang, Wenping; Narayanan, Vijaykrishnan; Xie, Yuan.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 539-544 1466222 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Yang S, Wolf W, Wang W, Narayanan V, Xie Y. Low-leakage robust SRAM cell design for sub-100nm technologies. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 539-544. 1466222. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).