Low-power and process variation tolerant memories in sub-90nm technologies

Saibal Mukhopadhyay, Swaroop Ghosh, Keejortg Kim, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-seale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self-repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub-90nm technologies.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages155-159
Number of pages5
ISBN (Print)0780397819, 9780780397811
DOIs
StatePublished - Jan 1 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Mukhopadhyay, S., Ghosh, S., Kim, K., & Roy, K. (2006). Low-power and process variation tolerant memories in sub-90nm technologies. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 155-159). [4063040] (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283871