Low power circuit techniques for fast carry-skip adders

Eric S. Gayles, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

A multi-level carry-skip addition scheme for static CMOS is presented which has O(lg n) asymptotic delay and has speed comparable to a carry-lookahead approach for typical operand bit precisions. However, the proposed architecture results in adders which dissipate nearly half the power of carry-lookahead adders. The proposed carry-skip method is also conflict free. This paper describes the proposed architecture and its circuit implementation, as well as the architecture's asymptotic worst case delay analysis. Also, empirical results comparing the adder's performance with other conventional architectures in a 0.5 μm CMOS process are provided.

Original languageEnglish (US)
Pages87-90
Number of pages4
StatePublished - Dec 1 1996
EventProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA
Duration: Aug 18 1996Aug 21 1996

Other

OtherProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3)
CityAmes, IA, USA
Period8/18/968/21/96

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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