Low power considerations in the design of pipelined FIR filters

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin

Research output: Contribution to conferencePaper

Abstract

This article discusses some design considerations in building deeply pipelined FIR filters using CMOS technology. The impact of these considerations on the area, speed and power dissipation of FIR filters is elaborated. Furthermore, detailed HOSPICE simulation results are presented to illustrate the relative power dissipations of the different approaches.

Original languageEnglish (US)
Pages32-33
Number of pages2
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE Symposium on Low Power Electronics - San Jose, CA, USA
Duration: Oct 9 1995Oct 11 1995

Other

OtherProceedings of the 1995 IEEE Symposium on Low Power Electronics
CitySan Jose, CA, USA
Period10/9/9510/11/95

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Nagendra, C., Owens, R. M., & Irwin, M. J. (1995). Low power considerations in the design of pipelined FIR filters. 32-33. Paper presented at Proceedings of the 1995 IEEE Symposium on Low Power Electronics, San Jose, CA, USA, .