Low-power high-speed current mode logic using Tunnel-FETs

Wei Yu Tsai, Huichu Liu, Xueqing Li, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Current mode logic (CML) circuits have been widely used in high-speed data transceivers. The lower-voltage-swing makes the switching speed of CML much higher than the static logic can achieve, so it is worthy to adopt the CML circuits at the cost of higher power consumption in the high-speed applications. In order to obtain a better power efficiency (Frequency/power) in CML, it is critical to reduce the power consumption while maintaining the high operating frequency. This paper proposes an alternative approach by building the CML circuits with tunneling-field-effect-transistor (Tunnel FETs or TFETs) to achieve a high-throughput, low-voltage interface circuit design. By taking advantage of its steep subthreshold slope (less than 60 mV/dec), TFET exhibits the same on/off current ratio at the input voltage swing interval much lower than that of the MOSFETs, which enables the supply voltage scaling in CML circuits. For a design target data-rate (20 Gbps for multiplexer and 50 Gbps for buffer), our simulations show that the proposed TFET CML circuits are able to reduce the supply voltage from 0.6 V in conventional Si FinFET CML circuits to as low as 0.3 V while using the same constant tail current. As a result, a power consumption reduction of approximately 50% is achieved by the proposed TFET CML circuits, making the TFET CML approach a promising candidate for future low-power, high-performance applications.

Original languageEnglish (US)
Title of host publication2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
EditorsLorena Garcia
PublisherIEEE Computer Society
EditionJanuary
ISBN (Electronic)9781479960163
DOIs
StatePublished - Jan 7 2015
Event2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico
Duration: Oct 6 2014Oct 8 2014

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
NumberJanuary
Volume2015-January
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
CountryMexico
CityPlaya del Carmen
Period10/6/1410/8/14

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Tsai, W. Y., Liu, H., Li, X., & Narayanan, V. (2015). Low-power high-speed current mode logic using Tunnel-FETs. In L. Garcia (Ed.), 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings (January ed.). [7004179] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-January, No. January). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2014.7004179