Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs

V. Saripalli, D. K. Mohata, S. Mookerjea, S. Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell [1] has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors to maintain state. In this paper, we introduce a p-type TFET with a degenerately doped source, which has a kT/q sub-threshold slope, compared to an n-type TFET which has a sub-kT/q slope. This difference in sub-threshold behaviour of the DDS PTFET and DDS NTFET helps to maintain the IOFF ratio which is required for cell stability. We explain the temperature dependent sub-threshold characteristics of the In0.53Ga 0.47As (DDS) p-TFET by analyzing the position of the Fermi level in the source of the p-TFET as a function of source doping. Further, the asymmetric source drain architecture of the TFETs is exploited to solve the adjacent bit flip problem of unselected Loadless 4T SRAM cells during a column write operation. Finally, we include a comparison of the leakage energy and cell access time of the TFET based SRAM cell and benchmark its performance relative to state-of-the-art CMOS based 6T SRAM cells.

Original languageEnglish (US)
Title of host publication68th Device Research Conference, DRC 2010
Pages101-102
Number of pages2
DOIs
StatePublished - Oct 11 2010
Event68th Device Research Conference, DRC 2010 - Notre Dame, IN, United States
Duration: Jun 21 2010Jun 23 2010

Other

Other68th Device Research Conference, DRC 2010
CountryUnited States
CityNotre Dame, IN
Period6/21/106/23/10

Fingerprint

Static random access storage
Field effect transistors
Tunnels
Leakage currents
Transistors
Fermi level
Doping (additives)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Saripalli, V., Mohata, D. K., Mookerjea, S., Datta, S., & Narayanan, V. (2010). Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs. In 68th Device Research Conference, DRC 2010 (pp. 101-102). [5551859] https://doi.org/10.1109/DRC.2010.5551859
Saripalli, V. ; Mohata, D. K. ; Mookerjea, S. ; Datta, S. ; Narayanan, Vijaykrishnan. / Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs. 68th Device Research Conference, DRC 2010. 2010. pp. 101-102
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abstract = "We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell [1] has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors to maintain state. In this paper, we introduce a p-type TFET with a degenerately doped source, which has a kT/q sub-threshold slope, compared to an n-type TFET which has a sub-kT/q slope. This difference in sub-threshold behaviour of the DDS PTFET and DDS NTFET helps to maintain the IOFF ratio which is required for cell stability. We explain the temperature dependent sub-threshold characteristics of the In0.53Ga 0.47As (DDS) p-TFET by analyzing the position of the Fermi level in the source of the p-TFET as a function of source doping. Further, the asymmetric source drain architecture of the TFETs is exploited to solve the adjacent bit flip problem of unselected Loadless 4T SRAM cells during a column write operation. Finally, we include a comparison of the leakage energy and cell access time of the TFET based SRAM cell and benchmark its performance relative to state-of-the-art CMOS based 6T SRAM cells.",
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Saripalli, V, Mohata, DK, Mookerjea, S, Datta, S & Narayanan, V 2010, Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs. in 68th Device Research Conference, DRC 2010., 5551859, pp. 101-102, 68th Device Research Conference, DRC 2010, Notre Dame, IN, United States, 6/21/10. https://doi.org/10.1109/DRC.2010.5551859

Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs. / Saripalli, V.; Mohata, D. K.; Mookerjea, S.; Datta, S.; Narayanan, Vijaykrishnan.

68th Device Research Conference, DRC 2010. 2010. p. 101-102 5551859.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Saripalli, V.

AU - Mohata, D. K.

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AU - Datta, S.

AU - Narayanan, Vijaykrishnan

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N2 - We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell [1] has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors to maintain state. In this paper, we introduce a p-type TFET with a degenerately doped source, which has a kT/q sub-threshold slope, compared to an n-type TFET which has a sub-kT/q slope. This difference in sub-threshold behaviour of the DDS PTFET and DDS NTFET helps to maintain the IOFF ratio which is required for cell stability. We explain the temperature dependent sub-threshold characteristics of the In0.53Ga 0.47As (DDS) p-TFET by analyzing the position of the Fermi level in the source of the p-TFET as a function of source doping. Further, the asymmetric source drain architecture of the TFETs is exploited to solve the adjacent bit flip problem of unselected Loadless 4T SRAM cells during a column write operation. Finally, we include a comparison of the leakage energy and cell access time of the TFET based SRAM cell and benchmark its performance relative to state-of-the-art CMOS based 6T SRAM cells.

AB - We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell [1] has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors to maintain state. In this paper, we introduce a p-type TFET with a degenerately doped source, which has a kT/q sub-threshold slope, compared to an n-type TFET which has a sub-kT/q slope. This difference in sub-threshold behaviour of the DDS PTFET and DDS NTFET helps to maintain the IOFF ratio which is required for cell stability. We explain the temperature dependent sub-threshold characteristics of the In0.53Ga 0.47As (DDS) p-TFET by analyzing the position of the Fermi level in the source of the p-TFET as a function of source doping. Further, the asymmetric source drain architecture of the TFETs is exploited to solve the adjacent bit flip problem of unselected Loadless 4T SRAM cells during a column write operation. Finally, we include a comparison of the leakage energy and cell access time of the TFET based SRAM cell and benchmark its performance relative to state-of-the-art CMOS based 6T SRAM cells.

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Saripalli V, Mohata DK, Mookerjea S, Datta S, Narayanan V. Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs. In 68th Device Research Conference, DRC 2010. 2010. p. 101-102. 5551859 https://doi.org/10.1109/DRC.2010.5551859