Low power robust finFET-based SRAM design in scaled technologies

Sumeet Kumar Gupta, Kaushik Roy

    Research output: Chapter in Book/Report/Conference proceedingChapter

    11 Scopus citations

    Abstract

    FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to superior gate control of the channel, lower short channel effects and higher scalability. However, width quantization in FinFETs constrains the design space of FinFET-based circuits, especially SRAMs in which transistor sizing is critical for the circuit robustness. The adverse effects of width quantization can be mitigated by appropriate device-circuit co-design of FinFETbased memories. This chapter describes some of such techniques with an emphasis on the device-circuit interactions associated with each methodology. The impact of different technology options in FinFETs like gate-underlap, fin orientation, fin height, gate workfunction and independent control of the gates on the stability, power and performance of 6 T SRAMs is discussed.

    Original languageEnglish (US)
    Title of host publicationCircuit Design for Reliability
    PublisherSpringer New York
    Pages223-253
    Number of pages31
    ISBN (Electronic)9781461440789
    ISBN (Print)9781461440772
    DOIs
    StatePublished - Jan 1 2015

    All Science Journal Classification (ASJC) codes

    • Engineering(all)

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  • Cite this

    Gupta, S. K., & Roy, K. (2015). Low power robust finFET-based SRAM design in scaled technologies. In Circuit Design for Reliability (pp. 223-253). Springer New York. https://doi.org/10.1007/978-1-4614-4078-9_11