Low power tradeoffs in signal processing hardware primitives

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and Manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and the constant time signed-digit adders.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on VLSI Signal Processing, Proceedings
Editors Anon
Pages276-285
Number of pages10
StatePublished - 1994
EventProceedings of the 1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Duration: Oct 26 1994Oct 28 1994

Other

OtherProceedings of the 1994 IEEE International Workshop VLSI Signal Processing
CityLa Jolla, CA, USA
Period10/26/9410/28/94

Fingerprint

Adders
Signal processing
Hardware
Digital signal processing

All Science Journal Classification (ASJC) codes

  • Signal Processing

Cite this

Nagendra, C., Owens, R. M., & Irwin, M. J. (1994). Low power tradeoffs in signal processing hardware primitives. In Anon (Ed.), IEEE Workshop on VLSI Signal Processing, Proceedings (pp. 276-285)
Nagendra, Chetana ; Owens, Robert Michael ; Irwin, Mary Jane. / Low power tradeoffs in signal processing hardware primitives. IEEE Workshop on VLSI Signal Processing, Proceedings. editor / Anon. 1994. pp. 276-285
@inproceedings{afa2bd25334849c895f72802e20e80d8,
title = "Low power tradeoffs in signal processing hardware primitives",
abstract = "In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and Manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and the constant time signed-digit adders.",
author = "Chetana Nagendra and Owens, {Robert Michael} and Irwin, {Mary Jane}",
year = "1994",
language = "English (US)",
pages = "276--285",
editor = "Anon",
booktitle = "IEEE Workshop on VLSI Signal Processing, Proceedings",

}

Nagendra, C, Owens, RM & Irwin, MJ 1994, Low power tradeoffs in signal processing hardware primitives. in Anon (ed.), IEEE Workshop on VLSI Signal Processing, Proceedings. pp. 276-285, Proceedings of the 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, 10/26/94.

Low power tradeoffs in signal processing hardware primitives. / Nagendra, Chetana; Owens, Robert Michael; Irwin, Mary Jane.

IEEE Workshop on VLSI Signal Processing, Proceedings. ed. / Anon. 1994. p. 276-285.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Low power tradeoffs in signal processing hardware primitives

AU - Nagendra, Chetana

AU - Owens, Robert Michael

AU - Irwin, Mary Jane

PY - 1994

Y1 - 1994

N2 - In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and Manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and the constant time signed-digit adders.

AB - In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and Manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and the constant time signed-digit adders.

UR - http://www.scopus.com/inward/record.url?scp=0028746383&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028746383&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028746383

SP - 276

EP - 285

BT - IEEE Workshop on VLSI Signal Processing, Proceedings

A2 - Anon, null

ER -

Nagendra C, Owens RM, Irwin MJ. Low power tradeoffs in signal processing hardware primitives. In Anon, editor, IEEE Workshop on VLSI Signal Processing, Proceedings. 1994. p. 276-285