Low power tradeoffs in signal processing hardware primitives

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper, we present extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing. The adders studied include the linear time ripple carry and Manchester carry chain adders, the logarithmic carry lookahead adders and its variations, the carry skip adder, and the constant time signed-digit adders.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on VLSI Signal Processing, Proceedings
Editors Anon
Pages276-285
Number of pages10
StatePublished - 1994
EventProceedings of the 1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Duration: Oct 26 1994Oct 28 1994

Other

OtherProceedings of the 1994 IEEE International Workshop VLSI Signal Processing
CityLa Jolla, CA, USA
Period10/26/9410/28/94

All Science Journal Classification (ASJC) codes

  • Signal Processing

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