Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In0.7Ga0.3As/GaAs0.35Sb 0.65 heterojunction tunneling field-effect transistor

Bijesh Rajamohanan; Dheeraj Mohata; Dmitry Zhernokletov; Barry Brennan; Robert M. Wallace; Roman Engel-Herbert; Suman Datta

doi:10.7567/APEX.6.101201

Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In_0.7Ga_0.3As/GaAs_0.35Sb _0.65 heterojunction tunneling field-effect transistor

Bijesh Rajamohanan, Dheeraj Mohata, Dmitry Zhernokletov, Barry Brennan, Robert M. Wallace, Roman Engel-Herbert, Suman Datta

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

The interface quality of a low temperature atomic-layer-deposited (ALD) HfO₂/Al₂O₃ bilayer high-Κ gate dielectric on a GaAs0.35Sb0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance- voltage characteristics and lower interface trap density in metal-oxide-semiconductor capacitor structures. Using the low-temperature ALD high-Κ dielectric, a GaAs_0.35Sb_0.65/In _0.7Ga_0.3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on-off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-Κ/GaAs _0.35Sb_0.65 interface.

Original language	English (US)
Article number	101201
Journal	Applied Physics Express
Volume	6
Issue number	10
DOIs	https://doi.org/10.7567/APEX.6.101201
State	Published - Oct 2013

All Science Journal Classification (ASJC) codes

Engineering(all)
Physics and Astronomy(all)

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@article{8a6f98e41a174253b50a32be96a318ae,

title = "Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In0.7Ga0.3As/GaAs0.35Sb 0.65 heterojunction tunneling field-effect transistor",

abstract = "The interface quality of a low temperature atomic-layer-deposited (ALD) HfO2/Al2O3 bilayer high-Κ gate dielectric on a GaAs0.35Sb0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance- voltage characteristics and lower interface trap density in metal-oxide-semiconductor capacitor structures. Using the low-temperature ALD high-Κ dielectric, a GaAs0.35Sb0.65/In 0.7Ga0.3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on-off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-Κ/GaAs 0.35Sb0.65 interface.",

author = "Bijesh Rajamohanan and Dheeraj Mohata and Dmitry Zhernokletov and Barry Brennan and Wallace, {Robert M.} and Roman Engel-Herbert and Suman Datta",

year = "2013",

month = oct,

doi = "10.7567/APEX.6.101201",

language = "English (US)",

volume = "6",

journal = "Applied Physics Express",

issn = "1882-0778",

publisher = "Japan Society of Applied Physics",

number = "10",

}

Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In_0.7Ga_0.3As/GaAs_0.35Sb _0.65 heterojunction tunneling field-effect transistor. / Rajamohanan, Bijesh; Mohata, Dheeraj; Zhernokletov, Dmitry; Brennan, Barry; Wallace, Robert M.; Engel-Herbert, Roman; Datta, Suman.

In: Applied Physics Express, Vol. 6, No. 10, 101201, 10.2013.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In0.7Ga0.3As/GaAs0.35Sb 0.65 heterojunction tunneling field-effect transistor

AU - Rajamohanan, Bijesh

AU - Mohata, Dheeraj

AU - Zhernokletov, Dmitry

AU - Brennan, Barry

AU - Wallace, Robert M.

AU - Engel-Herbert, Roman

AU - Datta, Suman

PY - 2013/10

Y1 - 2013/10

N2 - The interface quality of a low temperature atomic-layer-deposited (ALD) HfO2/Al2O3 bilayer high-Κ gate dielectric on a GaAs0.35Sb0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance- voltage characteristics and lower interface trap density in metal-oxide-semiconductor capacitor structures. Using the low-temperature ALD high-Κ dielectric, a GaAs0.35Sb0.65/In 0.7Ga0.3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on-off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-Κ/GaAs 0.35Sb0.65 interface.

AB - The interface quality of a low temperature atomic-layer-deposited (ALD) HfO2/Al2O3 bilayer high-Κ gate dielectric on a GaAs0.35Sb0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance- voltage characteristics and lower interface trap density in metal-oxide-semiconductor capacitor structures. Using the low-temperature ALD high-Κ dielectric, a GaAs0.35Sb0.65/In 0.7Ga0.3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on-off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-Κ/GaAs 0.35Sb0.65 interface.

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Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In_0.7Ga_0.3As/GaAs_0.35Sb _0.65 heterojunction tunneling field-effect transistor

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