Low-temperature atomic-layer-deposited high-Κ dielectric for p-channel In0.7Ga0.3As/GaAs0.35Sb 0.65 heterojunction tunneling field-effect transistor

Bijesh Rajamohanan, Dheeraj Mohata, Dmitry Zhernokletov, Barry Brennan, Robert M. Wallace, Roman Engel-Herbert, Suman Datta

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Abstract

The interface quality of a low temperature atomic-layer-deposited (ALD) HfO2/Al2O3 bilayer high-Κ gate dielectric on a GaAs0.35Sb0.65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 °C results in improved capacitance- voltage characteristics and lower interface trap density in metal-oxide-semiconductor capacitor structures. Using the low-temperature ALD high-Κ dielectric, a GaAs0.35Sb0.65/In 0.7Ga0.3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on-off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-Κ/GaAs 0.35Sb0.65 interface.

Original languageEnglish (US)
Article number101201
JournalApplied Physics Express
Volume6
Issue number10
DOIs
StatePublished - Oct 2013

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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