Low-temperature PEALD ZnO double-gate TFTs

Yuanyuan V. Li, J. Israel Ramirez, Haoyu U. Li, Thomas Nelson Jackson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We report double-gate ZnO thin film transistors fabricated using weak reactant plasma enhanced atomic layer deposition (PEALD) with a maximum process temperature of 200C. When operated as bottom gate only devices the TFTs have linear region mobility of 19 cm 2/Vs and the top gate can be used to vary the bottom-gate TFT threshold voltage by more than 2 V. With top and bottom gates connected together the linear region mobility increases to 24 cm 2/Vs, with a subthreshold slope of 160 mV/decade. The low process temperature of these devices allows simple fabrication on polyimide and other flexible polymeric substrates. Double gate TFTs are of interest to allow threshold voltage tuning, improved device performance and stability, and for circuit applications like mixers and analog circuits design. Double gate TFTs have been demonstrated using GIZO[1, 2]; however, these reports used a maximum process temperature of 350 C, too high for flexible polymeric substrates. We have previously reported high quality ZnO TFTs fabricated on both glass and plastic substrates using weak reactant PEALD with a maximum process temperature of 200 C[3, 4]. We now report double gate TFTs with the same maximum process temperature.

Original languageEnglish (US)
Title of host publication2011 International Semiconductor Device Research Symposium, ISDRS 2011
DOIs
StatePublished - Dec 1 2011
Event2011 International Semiconductor Device Research Symposium, ISDRS 2011 - College Park, MD, United States
Duration: Dec 7 2011Dec 9 2011

Publication series

Name2011 International Semiconductor Device Research Symposium, ISDRS 2011

Other

Other2011 International Semiconductor Device Research Symposium, ISDRS 2011
CountryUnited States
CityCollege Park, MD
Period12/7/1112/9/11

Fingerprint

Atomic layer deposition
Plasmas
Threshold voltage
Substrates
Temperature
Mixer circuits
Analog circuits
Thin film transistors
Polyimides
Tuning
Plastics
Fabrication
Glass
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, Y. V., Ramirez, J. I., Li, H. U., & Jackson, T. N. (2011). Low-temperature PEALD ZnO double-gate TFTs. In 2011 International Semiconductor Device Research Symposium, ISDRS 2011 [6135191] (2011 International Semiconductor Device Research Symposium, ISDRS 2011). https://doi.org/10.1109/ISDRS.2011.6135191
Li, Yuanyuan V. ; Ramirez, J. Israel ; Li, Haoyu U. ; Jackson, Thomas Nelson. / Low-temperature PEALD ZnO double-gate TFTs. 2011 International Semiconductor Device Research Symposium, ISDRS 2011. 2011. (2011 International Semiconductor Device Research Symposium, ISDRS 2011).
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Li, YV, Ramirez, JI, Li, HU & Jackson, TN 2011, Low-temperature PEALD ZnO double-gate TFTs. in 2011 International Semiconductor Device Research Symposium, ISDRS 2011., 6135191, 2011 International Semiconductor Device Research Symposium, ISDRS 2011, 2011 International Semiconductor Device Research Symposium, ISDRS 2011, College Park, MD, United States, 12/7/11. https://doi.org/10.1109/ISDRS.2011.6135191

Low-temperature PEALD ZnO double-gate TFTs. / Li, Yuanyuan V.; Ramirez, J. Israel; Li, Haoyu U.; Jackson, Thomas Nelson.

2011 International Semiconductor Device Research Symposium, ISDRS 2011. 2011. 6135191 (2011 International Semiconductor Device Research Symposium, ISDRS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - We report double-gate ZnO thin film transistors fabricated using weak reactant plasma enhanced atomic layer deposition (PEALD) with a maximum process temperature of 200C. When operated as bottom gate only devices the TFTs have linear region mobility of 19 cm 2/Vs and the top gate can be used to vary the bottom-gate TFT threshold voltage by more than 2 V. With top and bottom gates connected together the linear region mobility increases to 24 cm 2/Vs, with a subthreshold slope of 160 mV/decade. The low process temperature of these devices allows simple fabrication on polyimide and other flexible polymeric substrates. Double gate TFTs are of interest to allow threshold voltage tuning, improved device performance and stability, and for circuit applications like mixers and analog circuits design. Double gate TFTs have been demonstrated using GIZO[1, 2]; however, these reports used a maximum process temperature of 350 C, too high for flexible polymeric substrates. We have previously reported high quality ZnO TFTs fabricated on both glass and plastic substrates using weak reactant PEALD with a maximum process temperature of 200 C[3, 4]. We now report double gate TFTs with the same maximum process temperature.

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Li YV, Ramirez JI, Li HU, Jackson TN. Low-temperature PEALD ZnO double-gate TFTs. In 2011 International Semiconductor Device Research Symposium, ISDRS 2011. 2011. 6135191. (2011 International Semiconductor Device Research Symposium, ISDRS 2011). https://doi.org/10.1109/ISDRS.2011.6135191