Lower bound study on interconnect complexity of the decomposed finite state machines

W. L. Yang, R. M. Owens, M. J. Irwin

Research output: Contribution to journalArticle

Abstract

Various strategies for multiway general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic level implementation. In the paper the authors are concerned with the lower bound on the number of interconnecting wires that must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view, having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multiway decomposition of an arbitrary machine, and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are highly decomposable from an interconnect point of view.

Original languageEnglish (US)
Pages (from-to)332-336
Number of pages5
JournalIEE Proceedings: Computers and Digital Techniques
Volume142
Issue number5
DOIs
StatePublished - Sep 1 1995

Fingerprint

Finite automata
State Machine
Interconnect
Benchmark
Lower bound
Decomposition
Decompose
Decomposable
Cost functions
Cost Function
Wire
Logic
Costs
Arbitrary
Strategy

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

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Lower bound study on interconnect complexity of the decomposed finite state machines. / Yang, W. L.; Owens, R. M.; Irwin, M. J.

In: IEE Proceedings: Computers and Digital Techniques, Vol. 142, No. 5, 01.09.1995, p. 332-336.

Research output: Contribution to journalArticle

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