Abstract
Various strategies for multiway general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic level implementation. In the paper the authors are concerned with the lower bound on the number of interconnecting wires that must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view, having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multiway decomposition of an arbitrary machine, and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are highly decomposable from an interconnect point of view.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 332-336 |
| Number of pages | 5 |
| Journal | IEE Proceedings: Computers and Digital Techniques |
| Volume | 142 |
| Issue number | 5 |
| DOIs | |
| State | Published - Sep 1 1995 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
Cite this
}
Lower bound study on interconnect complexity of the decomposed finite state machines. / Yang, W. L.; Owens, R. M.; Irwin, M. J.
In: IEE Proceedings: Computers and Digital Techniques, Vol. 142, No. 5, 01.09.1995, p. 332-336.Research output: Contribution to journal › Article
TY - JOUR
T1 - Lower bound study on interconnect complexity of the decomposed finite state machines
AU - Yang, W. L.
AU - Owens, R. M.
AU - Irwin, M. J.
PY - 1995/9/1
Y1 - 1995/9/1
N2 - Various strategies for multiway general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic level implementation. In the paper the authors are concerned with the lower bound on the number of interconnecting wires that must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view, having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multiway decomposition of an arbitrary machine, and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are highly decomposable from an interconnect point of view.
AB - Various strategies for multiway general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic level implementation. In the paper the authors are concerned with the lower bound on the number of interconnecting wires that must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view, having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multiway decomposition of an arbitrary machine, and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are highly decomposable from an interconnect point of view.
UR - http://www.scopus.com/inward/record.url?scp=0029370735&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029370735&partnerID=8YFLogxK
U2 - 10.1049/ip-cdt:19952127
DO - 10.1049/ip-cdt:19952127
M3 - Article
AN - SCOPUS:0029370735
VL - 142
SP - 332
EP - 336
JO - IEE Proceedings: Computers and Digital Techniques
JF - IEE Proceedings: Computers and Digital Techniques
SN - 1350-2387
IS - 5
ER -