Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops

Xueqing Li, Sumitha George, Yuhua Liang, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Kumar Gupta, John Sampson, Meng Fan Chang, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (BR), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule BR energy. This new nvDFF promises area-and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications.

Original languageEnglish (US)
Pages (from-to)2670-2674
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume65
Issue number6
DOIs
StatePublished - Jun 2018

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Li, X., George, S., Liang, Y., Ma, K., Ni, K., Aziz, A., Gupta, S. K., Sampson, J., Chang, M. F., Liu, Y., Yang, H., Datta, S., & Narayanan, V. (2018). Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops. IEEE Transactions on Electron Devices, 65(6), 2670-2674. https://doi.org/10.1109/TED.2018.2829348