Manufacturing methods employing molecular ruler lithography

Shyamala Subramanian, Jeffrey M. Catchmark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


Molecular ruler nanolithography has the potential to become a commercially viable approach for reducing the feature sizes of structures fabricated using conventional optical or electron beam lithography by employing chemical self assembly techniques. In this process engineered organic molecules of precise length are systematically assembled onto functional host structures to create a template for producing features of reduced dimensions. Improved yield of daughter features and reproducibility of feature sizes are two key issues to be addressed in order to make this process compatible for the industry. Also gold, which is a commonly used parent host, has high diffusivity in silicon, thus requiring careful use in integrated circuit manufacturing. Another limitation of this process is that the thickness of the daughter feature has to be fabricated less than the thickness of the molecular resist in order to get a reproducible lift-off. Here molecular ruler lithography techniques are reviewed including a novel method for implementing molecular ruler nanolithography using a sacrificial multilayer host structure which aims to address the above issues. In this method a sacrificial lift-off resist (LOR) is selectively placed underneath the parent structure to create a sacrificial multilayer host stack. This facilitates the easy and preferential removal of the parent metal, leaving behind the isolated daughter features whose dimensions have been reduced with respect to the host via the molecular ruler method. This lift off process is seen to produce uniform feature sizes with the potential for high yield and reproducibility. The gold host in this modified process is always isolated from the substrate (in this case, silicon) surface via the LOR (Micr°Chem Corp) and the daughter feature thickness is dependant on the thickness of the LOR layer and thus can be easily increased.

Original languageEnglish (US)
Title of host publicationProceedings - 2005 International Symposium on Microelectronics, IMAPS 2005
Number of pages6
StatePublished - Dec 1 2005
Event38th International Symposium on Microelectronics, IMAPS 2005 - Philadelphia, PA, United States
Duration: Sep 25 2005Sep 29 2005

Publication series

NameProceedings - 2005 International Symposium on Microelectronics, IMAPS 2005


Other38th International Symposium on Microelectronics, IMAPS 2005
CountryUnited States
CityPhiladelphia, PA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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