Mapping high-dimension wavefront computations to silicon

Chen Mie Wu, Robert M. Owens, Mary J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The authors present a new template-matching algorithm with good recognition performance. However, this new algorithm exhibits a complex, four-dimensional, wavefront architecture. Thus, for VLSI implementation, reduced architectures with fewer connections and processors need to be derived. For this purpose, the authors develop a systematic reduction methodology to manually map wavefront computations from high-dimension to low-dimension. This methodology consists of seven steps. Based on this methodology, the authors derive several two-dimensional architectures which are suitable for VLSI implementation for the new template-matching algorithm and have simulated one of the architectures by using the Intel Hypercube Machine iPSC/2.

Original languageEnglish (US)
Title of host publicationProc 90 Int Conf Appl Specif Array Process
PublisherPubl by IEEE
Pages78-89
Number of pages12
ISBN (Print)0818690895
StatePublished - Jan 1 1991
EventProceedings of the 1990 International Conference on Application Specific Array Processors - Princeton, NJ, USA
Duration: Sep 5 1990Sep 7 1990

Publication series

NameProc 90 Int Conf Appl Specif Array Process

Other

OtherProceedings of the 1990 International Conference on Application Specific Array Processors
CityPrinceton, NJ, USA
Period9/5/909/7/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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