With an increasing focus on low power computing devices such as PDA's, energy has become an important criterion for optimization. Power mode control of memory devices has the potential to significantly reduce energy consumption, for a moderate increase in execution time. Prior studies have explored the benefits of many schemes for DRAM power mode control. In this work, we present a framework for estimating the optimal energy savings that can be obtained under various constraints. We also analyze the memory energy consumption patterns of a set of benchmarks drawn from the SPEC2000 suite and establish that energy consumed during power mode transitions is a significant component of DRAM energy. We characterize the memory access behavior of these benchmarks by studying their inter access times. Based on our analysis, we revisit existing mode control schemes and fine tune their performance. In particular we propose a history based mode control policy, which performs better than the existing schemes in most cases.