Memory system energy: Influence of hardware-software optimizations

G. Esakkimuthu, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalConference article

8 Scopus citations

Abstract

Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms (block buffering and sub-banking) and three widely used compiler optimization techniques (linear loop transformation, loop tiling, and loop unrolling). Our results show that the pure hardware optimizations (eight block buffers and four sub-banks in a 4 K, 2-way cache) provided up to 4% energy saving, with an average saving of 2% across all benchmarks. In contrast, the pure software optimization approach that uses all three compiler optimizations, provided at least 23% energy saving, with an average of 62%. However, a closer observation reveals that hardware optimization becomes more critical for on-chip cache energy reduction when executing optimized codes.

Original languageEnglish (US)
Pages (from-to)244-246
Number of pages3
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 3 2000
EventProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00 - Portacino Coast, Italy
Duration: Jul 26 2000Jul 27 2000

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

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