Methodologies to exploit ATPG tools for de-camouflaging

Deepakreddy Vontela, Swaroop Ghosh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Scopus citations

    Abstract

    Semiconductor supply chain is increasingly getting exposed to Reverse Engineering (RE) of Intellectual Property (IP). Camouflaging of gates are typically employed to hide the gate functionality to prevent RE. Adversaries perform RE by developing custom software to determine test patterns and analyze the outputs. In this paper, we show that RE of camouflaged design can be performed by exploiting the test features of commercial/publicly available Automatic Test Pattern Generation (ATPG) tools. We also propose a controllability/observability and Hamming Distance sensitivity based metric to select target gates for camouflaging. Our simulation shows that the proposed techniques can increase the RE effort significantly by camouflaging small fraction of gates.

    Original languageEnglish (US)
    Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
    PublisherIEEE Computer Society
    Pages250-256
    Number of pages7
    ISBN (Electronic)9781509054046
    DOIs
    StatePublished - May 2 2017
    Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
    Duration: Mar 14 2017Mar 15 2017

    Publication series

    NameProceedings - International Symposium on Quality Electronic Design, ISQED
    ISSN (Print)1948-3287
    ISSN (Electronic)1948-3295

    Other

    Other18th International Symposium on Quality Electronic Design, ISQED 2017
    CountryUnited States
    CitySanta Clara
    Period3/14/173/15/17

    All Science Journal Classification (ASJC) codes

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

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