MGAP family of processor arrays

Kevin Acken; Eric Gayles; Tom Kelliher; Robert M. Owens; Mary Jane Irwin

MGAP family of processor arrays

Kevin Acken, Eric Gayles, Tom Kelliher, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journal › Article › peer-review

Abstract

The Micro-Grain Array Processor (MGAP) is a family of massively parallel SIMD arrays of fine grain processing elements powerful enough to perform complex signal and image processing algorithms in real time. The MGAP was also designed to be compact enough to conveniently fit as an add-on board to a standard workstation at a fraction of the development cost of other comparable parallel machines. In this paper we update the status of the MGAP-2, which became operational in October 1996, and present a comparison of the MGAP-1 and the MGAP-2. We also give performance comparisons of the two designs through three popular image/video compression algorithms: the Discrete Cosine Transform, Motion Estimation, and Fractal Compression.

Original language	English (US)
Pages (from-to)	105-110
Number of pages	6
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 1997

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

Fingerprint Dive into the research topics of 'MGAP family of processor arrays'. Together they form a unique fingerprint.

Cite this

@article{eadd753d64c54db9b00dd4a9c9d5c495,

title = "MGAP family of processor arrays",

abstract = "The Micro-Grain Array Processor (MGAP) is a family of massively parallel SIMD arrays of fine grain processing elements powerful enough to perform complex signal and image processing algorithms in real time. The MGAP was also designed to be compact enough to conveniently fit as an add-on board to a standard workstation at a fraction of the development cost of other comparable parallel machines. In this paper we update the status of the MGAP-2, which became operational in October 1996, and present a comparison of the MGAP-1 and the MGAP-2. We also give performance comparisons of the two designs through three popular image/video compression algorithms: the Discrete Cosine Transform, Motion Estimation, and Fractal Compression.",

author = "Kevin Acken and Eric Gayles and Tom Kelliher and Owens, {Robert M.} and Irwin, {Mary Jane}",

year = "1997",

language = "English (US)",

pages = "105--110",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - MGAP family of processor arrays

AU - Acken, Kevin

AU - Gayles, Eric

AU - Kelliher, Tom

AU - Owens, Robert M.

AU - Irwin, Mary Jane

PY - 1997

Y1 - 1997

N2 - The Micro-Grain Array Processor (MGAP) is a family of massively parallel SIMD arrays of fine grain processing elements powerful enough to perform complex signal and image processing algorithms in real time. The MGAP was also designed to be compact enough to conveniently fit as an add-on board to a standard workstation at a fraction of the development cost of other comparable parallel machines. In this paper we update the status of the MGAP-2, which became operational in October 1996, and present a comparison of the MGAP-1 and the MGAP-2. We also give performance comparisons of the two designs through three popular image/video compression algorithms: the Discrete Cosine Transform, Motion Estimation, and Fractal Compression.

AB - The Micro-Grain Array Processor (MGAP) is a family of massively parallel SIMD arrays of fine grain processing elements powerful enough to perform complex signal and image processing algorithms in real time. The MGAP was also designed to be compact enough to conveniently fit as an add-on board to a standard workstation at a fraction of the development cost of other comparable parallel machines. In this paper we update the status of the MGAP-2, which became operational in October 1996, and present a comparison of the MGAP-1 and the MGAP-2. We also give performance comparisons of the two designs through three popular image/video compression algorithms: the Discrete Cosine Transform, Motion Estimation, and Fractal Compression.

UR - http://www.scopus.com/inward/record.url?scp=0030713527&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030713527&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0030713527

SP - 105

EP - 110

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

SN - 1066-1395

ER -