MIRA: A multi-layered on-chip interconnect router architecture

Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Vijaykrishnan Narayanan, Chitaranjan Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

158 Citations (Scopus)

Abstract

Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

Original languageEnglish (US)
Title of host publicationISCA 2008, Proceedings - 35th International Symposium on Computer Architecture
Pages251-261
Number of pages11
DOIs
StatePublished - Oct 1 2008
EventISCA 2008, 35th International Symposium on Computer Architecture - Beijing, China
Duration: Jun 21 2008Jun 25 2008

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

OtherISCA 2008, 35th International Symposium on Computer Architecture
CountryChina
CityBeijing
Period6/21/086/25/08

Fingerprint

Routers
Electric power utilization
Network-on-chip
Simulators

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Park, D., Eachempati, S., Das, R., Mishra, A. K., Xie, Y., Narayanan, V., & Das, C. (2008). MIRA: A multi-layered on-chip interconnect router architecture. In ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture (pp. 251-261). [4556731] (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1109/ISCA.2008.13
Park, Dongkook ; Eachempati, Soumya ; Das, Reetuparna ; Mishra, Asit K. ; Xie, Yuan ; Narayanan, Vijaykrishnan ; Das, Chitaranjan. / MIRA : A multi-layered on-chip interconnect router architecture. ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture. 2008. pp. 251-261 (Proceedings - International Symposium on Computer Architecture).
@inproceedings{74fdd851931f49e683ed5178b30bc857,
title = "MIRA: A multi-layered on-chip interconnect router architecture",
abstract = "Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and na{\"i}ve 3D designs in terms of performance and power. It can achieve up to 42{\%} reduction in power consumption and up to 51{\%} improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67{\%} and 38{\%}, respectively.",
author = "Dongkook Park and Soumya Eachempati and Reetuparna Das and Mishra, {Asit K.} and Yuan Xie and Vijaykrishnan Narayanan and Chitaranjan Das",
year = "2008",
month = "10",
day = "1",
doi = "10.1109/ISCA.2008.13",
language = "English (US)",
isbn = "9780769531748",
series = "Proceedings - International Symposium on Computer Architecture",
pages = "251--261",
booktitle = "ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture",

}

Park, D, Eachempati, S, Das, R, Mishra, AK, Xie, Y, Narayanan, V & Das, C 2008, MIRA: A multi-layered on-chip interconnect router architecture. in ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture., 4556731, Proceedings - International Symposium on Computer Architecture, pp. 251-261, ISCA 2008, 35th International Symposium on Computer Architecture, Beijing, China, 6/21/08. https://doi.org/10.1109/ISCA.2008.13

MIRA : A multi-layered on-chip interconnect router architecture. / Park, Dongkook; Eachempati, Soumya; Das, Reetuparna; Mishra, Asit K.; Xie, Yuan; Narayanan, Vijaykrishnan; Das, Chitaranjan.

ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture. 2008. p. 251-261 4556731 (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - MIRA

T2 - A multi-layered on-chip interconnect router architecture

AU - Park, Dongkook

AU - Eachempati, Soumya

AU - Das, Reetuparna

AU - Mishra, Asit K.

AU - Xie, Yuan

AU - Narayanan, Vijaykrishnan

AU - Das, Chitaranjan

PY - 2008/10/1

Y1 - 2008/10/1

N2 - Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

AB - Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

UR - http://www.scopus.com/inward/record.url?scp=52649135185&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=52649135185&partnerID=8YFLogxK

U2 - 10.1109/ISCA.2008.13

DO - 10.1109/ISCA.2008.13

M3 - Conference contribution

AN - SCOPUS:52649135185

SN - 9780769531748

T3 - Proceedings - International Symposium on Computer Architecture

SP - 251

EP - 261

BT - ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture

ER -

Park D, Eachempati S, Das R, Mishra AK, Xie Y, Narayanan V et al. MIRA: A multi-layered on-chip interconnect router architecture. In ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture. 2008. p. 251-261. 4556731. (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1109/ISCA.2008.13