Mitigating electromigration of power supply networks using bidirectional current stress

Jing Xie, Vijaykrishnan Narayanan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Electromigration (EM) is one of the major reliability issues for IC designs. The EM effect is observed as the shape change of metal wires under uni-directional high density current. Such metal wire distortions could result in open-circuit failures or short-circuit failures for the interconnects in integrated circuits. The current density on power supply network is usually the highest one among all the on-chip interconnects, and the current direction on power rails seldom changes. Consequently, the power supply network is the most EM-vulnerable component on a chip. We propose a novel solution based on the electromigration AC healing effect to extend the lifetime of power supply networks. This solution uses simple control logics to apply balanced amount of current in both directions of power rails. Therefore, power wires can perform self-healing during function mode. This technique can be easily integrated into different package plans with small area and performance overhead. The post layout simulation shows 3X-10X increase of the mean time to failure (MTTF) for the power rails.

Original languageEnglish (US)
Title of host publicationGLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012
Pages299-302
Number of pages4
DOIs
StatePublished - May 22 2012
Event22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT, United States
Duration: May 3 2012May 4 2012

Other

Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
CountryUnited States
CitySalt Lake City, UT
Period5/3/125/4/12

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Xie, J., Narayanan, V., & Xie, Y. (2012). Mitigating electromigration of power supply networks using bidirectional current stress. In GLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012 (pp. 299-302) https://doi.org/10.1145/2206781.2206854