Mitigating thermal effects on clock skew with dynamically adaptive drivers

Mosin Mondai, Andrew Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, Vijaykrishnan Narayanan, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance.

Original languageEnglish (US)
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Pages67-72
Number of pages6
DOIs
StatePublished - Aug 28 2007
Event8th International Symposium on Quality Electronic Design, ISQED 2007 - San Jose, CA, United States
Duration: Mar 26 2007Mar 28 2007

Publication series

NameProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Other

Other8th International Symposium on Quality Electronic Design, ISQED 2007
CountryUnited States
CitySan Jose, CA
Period3/26/073/28/07

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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