MLC PCM main memory with accelerated read

Mohammad Arjomand, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper alleviates the problem of slow reads in the Multi-Level Cell Phase Change Memory (MLC PCM) by exploiting a the fact that the Most-Significant Bit (MSB) of MLCs is read fast, while reading the Least-Significant Bits (LSBs) is slower. We propose Half-Line PCM (HL-PCM), a memory architecture that leverages this property to send half of a cache line to the processor ahead of the other half, so that processor continues its execution if the missed data element is in the first half. Our evaluation shows that HL-PCM improves program execution time by 23%, on average, in a 16-core CMP model for workloads from PARSEC-2 benchmark.

Original languageEnglish (US)
Title of host publicationISPASS 2016 - International Symposium on Performance Analysis of Systems and Software
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages143-144
Number of pages2
ISBN (Electronic)9781509019526
DOIs
StatePublished - May 31 2016
Event17th International Symposium on Performance Analysis of Systems and Software, ISPASS 2016 - Uppsala, Sweden
Duration: Apr 17 2016Apr 19 2016

Publication series

NameISPASS 2016 - International Symposium on Performance Analysis of Systems and Software

Other

Other17th International Symposium on Performance Analysis of Systems and Software, ISPASS 2016
CountrySweden
CityUppsala
Period4/17/164/19/16

All Science Journal Classification (ASJC) codes

  • Software
  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture

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