Modeling steep slope devices: From circuits to architectures

Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Steep Slope devices, with Heterojunction Tunnel FETs (TFETs) in particular, have been proposed as a viable solution to overcome the subthreshold slope limitation in existing CMOS technology and achieve ultra-low voltage operation with acceptable performance. However, state-of-the-art FinFET technologies continue to demonstrate superior performance than steep slope devices in application domains demanding peak single threaded performance. In this context, we examine different computing paradigms where TFET technologies can be used, not just as a 'drop in' replacement, but as an additional parameter to augment the architectural design space. This greatly widens the scope of optimizations for performance and power. We investigate the tradeoffs between device and architectures in general purpose processors when performance, power and temperature are individually constrained. We also synthesize examples of domain-specific accelerators used in computer vision using in-house TFET standard cell libraries to demonstrate the energy benefits of designing TFET-based accelerators. We demonstrate that synthesizing these accelerators using TFETs reduces energy by over 6X in comparison to an equivalent isovoltage CMOS-based design and by over 30% in comparison to an iso-performance CMOS design.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
Publication statusPublished - Jan 1 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: Mar 24 2014Mar 28 2014

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period3/24/143/28/14

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Swaminathan, K., Kim, M. S., Chandramoorthy, N., Sedighi, B., Perricone, R., Sampson, J., & Narayanan, V. (2014). Modeling steep slope devices: From circuits to architectures. In Proceedings - Design, Automation and Test in Europe, DATE 2014 [6800350] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/DATE2014.149