Monolithic 3D enabled processing-in-SRAM memory

Vijaykrishnan Narayanan; Nagadastagiri Challapalle; Ikenna Okafor; Srivatsa Srinivasa; Nicholas Jao

doi:10.1109/CSTIC49141.2020.9282479

Monolithic 3D enabled processing-in-SRAM memory

Vijaykrishnan Narayanan, Nagadastagiri Challapalle, Ikenna Okafor, Srivatsa Srinivasa, Nicholas Jao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work will provide an overview of recent advances in enabling SRAM-based compute fabrics leveraging monolithic 3D (M3D). It will highlight that the fine grain connectivity enabled by M3D, enables to embed computations close to the memory cells significantly reducing the data transfer costs. The application level benefits to emerging workloads will also be presented.

Original language	English (US)
Title of host publication	China Semiconductor Technology International Conference 2020, CSTIC 2020
Editors	Cor Claeys, Steve Liang, Qinghuang Lin, Ru Huang, Hanming Wu, Peilin Song, Kafai Lai, Ying Zhang, Beichao Zhang, Xinping Qu, Hsiang-Lan Lung, Wenjian Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728165585
DOIs	https://doi.org/10.1109/CSTIC49141.2020.9282479
State	Published - Jun 26 2020
Event	2020 China Semiconductor Technology International Conference, CSTIC 2020 - Shanghai, China Duration: Jun 26 2020 → Jul 17 2020

Publication series

Name	China Semiconductor Technology International Conference 2020, CSTIC 2020

Conference

Conference	2020 China Semiconductor Technology International Conference, CSTIC 2020
Country/Territory	China
City	Shanghai
Period	6/26/20 → 7/17/20

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/CSTIC49141.2020.9282479

Cite this

Narayanan, V., Challapalle, N., Okafor, I., Srinivasa, S., & Jao, N. (2020). Monolithic 3D enabled processing-in-SRAM memory. In C. Claeys, S. Liang, Q. Lin, R. Huang, H. Wu, P. Song, K. Lai, Y. Zhang, B. Zhang, X. Qu, H-L. Lung, & W. Yu (Eds.), China Semiconductor Technology International Conference 2020, CSTIC 2020 [9282479] (China Semiconductor Technology International Conference 2020, CSTIC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSTIC49141.2020.9282479

Narayanan, Vijaykrishnan ; Challapalle, Nagadastagiri ; Okafor, Ikenna et al. / Monolithic 3D enabled processing-in-SRAM memory. China Semiconductor Technology International Conference 2020, CSTIC 2020. editor / Cor Claeys ; Steve Liang ; Qinghuang Lin ; Ru Huang ; Hanming Wu ; Peilin Song ; Kafai Lai ; Ying Zhang ; Beichao Zhang ; Xinping Qu ; Hsiang-Lan Lung ; Wenjian Yu. Institute of Electrical and Electronics Engineers Inc., 2020. (China Semiconductor Technology International Conference 2020, CSTIC 2020).

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title = "Monolithic 3D enabled processing-in-SRAM memory",

abstract = "This work will provide an overview of recent advances in enabling SRAM-based compute fabrics leveraging monolithic 3D (M3D). It will highlight that the fine grain connectivity enabled by M3D, enables to embed computations close to the memory cells significantly reducing the data transfer costs. The application level benefits to emerging workloads will also be presented. ",

author = "Vijaykrishnan Narayanan and Nagadastagiri Challapalle and Ikenna Okafor and Srivatsa Srinivasa and Nicholas Jao",

note = "Funding Information: This work was supported in part by Semiconductor Research Corporation (SRC) Center for Brain-inspired Computing Enabling Autonomous Intelligence (C-BRIC) and Center for Research in Intelligent Storage and Processing in Memory (CRSP). Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 China Semiconductor Technology International Conference, CSTIC 2020 ; Conference date: 26-06-2020 Through 17-07-2020",

year = "2020",

month = jun,

day = "26",

doi = "10.1109/CSTIC49141.2020.9282479",

language = "English (US)",

series = "China Semiconductor Technology International Conference 2020, CSTIC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Cor Claeys and Steve Liang and Qinghuang Lin and Ru Huang and Hanming Wu and Peilin Song and Kafai Lai and Ying Zhang and Beichao Zhang and Xinping Qu and Hsiang-Lan Lung and Wenjian Yu",

booktitle = "China Semiconductor Technology International Conference 2020, CSTIC 2020",

address = "United States",

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Narayanan, V, Challapalle, N, Okafor, I, Srinivasa, S & Jao, N 2020, Monolithic 3D enabled processing-in-SRAM memory. in C Claeys, S Liang, Q Lin, R Huang, H Wu, P Song, K Lai, Y Zhang, B Zhang, X Qu, H-L Lung & W Yu (eds), China Semiconductor Technology International Conference 2020, CSTIC 2020., 9282479, China Semiconductor Technology International Conference 2020, CSTIC 2020, Institute of Electrical and Electronics Engineers Inc., 2020 China Semiconductor Technology International Conference, CSTIC 2020, Shanghai, China, 6/26/20. https://doi.org/10.1109/CSTIC49141.2020.9282479

Monolithic 3D enabled processing-in-SRAM memory. / Narayanan, Vijaykrishnan; Challapalle, Nagadastagiri; Okafor, Ikenna et al.

China Semiconductor Technology International Conference 2020, CSTIC 2020. ed. / Cor Claeys; Steve Liang; Qinghuang Lin; Ru Huang; Hanming Wu; Peilin Song; Kafai Lai; Ying Zhang; Beichao Zhang; Xinping Qu; Hsiang-Lan Lung; Wenjian Yu. Institute of Electrical and Electronics Engineers Inc., 2020. 9282479 (China Semiconductor Technology International Conference 2020, CSTIC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Monolithic 3D enabled processing-in-SRAM memory

AU - Narayanan, Vijaykrishnan

AU - Challapalle, Nagadastagiri

AU - Okafor, Ikenna

AU - Srinivasa, Srivatsa

AU - Jao, Nicholas

N1 - Funding Information: This work was supported in part by Semiconductor Research Corporation (SRC) Center for Brain-inspired Computing Enabling Autonomous Intelligence (C-BRIC) and Center for Research in Intelligent Storage and Processing in Memory (CRSP). Publisher Copyright: © 2020 IEEE.

PY - 2020/6/26

Y1 - 2020/6/26

N2 - This work will provide an overview of recent advances in enabling SRAM-based compute fabrics leveraging monolithic 3D (M3D). It will highlight that the fine grain connectivity enabled by M3D, enables to embed computations close to the memory cells significantly reducing the data transfer costs. The application level benefits to emerging workloads will also be presented.

AB - This work will provide an overview of recent advances in enabling SRAM-based compute fabrics leveraging monolithic 3D (M3D). It will highlight that the fine grain connectivity enabled by M3D, enables to embed computations close to the memory cells significantly reducing the data transfer costs. The application level benefits to emerging workloads will also be presented.

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DO - 10.1109/CSTIC49141.2020.9282479

M3 - Conference contribution

AN - SCOPUS:85099243795

T3 - China Semiconductor Technology International Conference 2020, CSTIC 2020

BT - China Semiconductor Technology International Conference 2020, CSTIC 2020

A2 - Claeys, Cor

A2 - Liang, Steve

A2 - Lin, Qinghuang

A2 - Huang, Ru

A2 - Wu, Hanming

A2 - Song, Peilin

A2 - Lai, Kafai

A2 - Zhang, Ying

A2 - Zhang, Beichao

A2 - Qu, Xinping

A2 - Lung, Hsiang-Lan

A2 - Yu, Wenjian

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 China Semiconductor Technology International Conference, CSTIC 2020

Y2 - 26 June 2020 through 17 July 2020

ER -

Narayanan V, Challapalle N, Okafor I, Srinivasa S, Jao N. Monolithic 3D enabled processing-in-SRAM memory. In Claeys C, Liang S, Lin Q, Huang R, Wu H, Song P, Lai K, Zhang Y, Zhang B, Qu X, Lung H-L, Yu W, editors, China Semiconductor Technology International Conference 2020, CSTIC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9282479. (China Semiconductor Technology International Conference 2020, CSTIC 2020). doi: 10.1109/CSTIC49141.2020.9282479

Monolithic 3D enabled processing-in-SRAM memory

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