Monolithic 3D+-IC based Reconfigurable Compute-in-Memory SRAM Macro

Srivatsa Srinivasa, Yung Ning Tu, Xin Si, Cheng Xin Xue, Chun Ying Lee, Fu Kuo Hsueh, Chane Hone Shen, Jia Min Shieh, Wen Kuan Yeh, Akshay Krishna Ramanathan, Mon Shu Ho, John Morgan Sampson, Meng Fan Chang, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V Vddmin 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.

Original languageEnglish (US)
Title of host publication2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT32-T33
ISBN (Electronic)9784863487178
DOIs
StatePublished - Jun 1 2019
Event39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan
Duration: Jun 9 2019Jun 14 2019

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2019-June
ISSN (Print)0743-1562

Conference

Conference39th Symposium on VLSI Technology, VLSI Technology 2019
CountryJapan
CityKyoto
Period6/9/196/14/19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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