Morphable cache architectures: Potential benefits

I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. Ramanujamy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Computer architects ha ve tried to mitigate the consequences of high memory latencies using a variety techniques. An example of these techniques is m ulti-lev elcaches to counteract the latency that results from having a memory that is slower than the processor. Recent research has demonstrated that compiler optimizations that modify data layouts and restructure computation can be successful in improving memory system performance. However, in many cases, working with a fixed cache configuration prevents the application/compiler from obtaining the maximum performance. In addition, prompted by demands in portabilit y, long battery life, and low-cost packaging, the computer industry has started viewing energy and power as decisive design factors, along with performance and cost. This makes the job of the compiler/user even more dificult as one needs to strik e a balance between low power/energy consumption and high performance. Consequently, adapting the code to the underlying cache/memory hierarchy is becoming more and more dificult. In this paper, we tak e an alternate approach and attempt to adapt the cache arc hitecture to the software needs. We focus on array-dominated applications and measure the potential benefits that could be gained from a morphable (reconfigurable) cache architecture. Our results show that not only different applications work best with different cache configurations, but also that different loop nests in a given application demand different configurations. Our results also indicate that the most suitable cache configuration for a giv en application or a single nest depends strongly on the ob-jectiv e function being optimized. For example, minimizing cache memory energy requires a different cache configuration for each nest than an objective which tries to minimize the overall memory system energy. Based on our experiments, we conclude that fine-grain (loop nest-level) cache configuration management is an important step for a solution to the challenging architecture/software tradeoffs awaiting system designers in the future.

Original languageEnglish (US)
Title of host publicationLCTES 2001 - Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems
PublisherAssociation for Computing Machinery, Inc
Pages128-137
Number of pages10
ISBN (Electronic)1581134258, 9781581134254
DOIs
StatePublished - Aug 1 2001
Event2001 ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2001 - Snow Bird, United States
Duration: Jun 22 2001Jun 23 2001

Publication series

NameLCTES 2001 - Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems

Other

Other2001 ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2001
CountryUnited States
CitySnow Bird
Period6/22/016/23/01

All Science Journal Classification (ASJC) codes

  • Software

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