MorphCache: A reconfigurable adaptive multi-level cache hierarchy

Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut Kandemir, Mary Jane Irwin, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Given the diverse range of application characteristics that chip multiprocessors (CMPs) need to cater to, a "one-cache-topology-fits- all" design philosophy will clearly be inadequate. In this paper, we propose MorphCache, a Reconfigurable Adaptive Multi-level Cache hierarchy. Mor-phCache dynamically tunes a multi-level cache topology in a CMP to allow significantly different cache topologies to exist on the same architecture. Starting from per-core L2 and L3 cache slices as the basic design point, MorphCache alters the cache topology dynamically by merging or splitting cache slices and modifying the accessibility of different cache slice groups to different cores in a CMP. We evaluated MorphCache on a 16 core CMP on a full system simulator and found that it significantly improves both average throughput and harmonic mean of speedups of diverse multithreaded and multiprogrammed workloads. Specifically, our results show that MorphCache improves throughput of the multiprogrammed mixes by 29.9% over a topology with all-shared L2 and L3 caches and 27.9% over a topology with per core private L2 cache and shared L3 cache. In addition, we also compared MorphCache to partitioning a single shared cache at each level using promotion/insertion pseudo-partitioning (PIPP) [28] and managing per-core private cache at each level using dynamic spill receive caches (DSR) [18]. We found that MorphCache improves average throughput by 6.6% over PIPP and by 5.7% over DSR when applied to both L2 and L3 caches.

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Pages231-242
Number of pages12
DOIs
StatePublished - May 17 2011
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other17th International Symposium on High-Performance Computer Architecture, HPCA 2011
CountryUnited States
CitySan Antonio, TX
Period2/12/112/16/11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Srikantaiah, S., Kultursay, E., Zhang, T., Kandemir, M., Irwin, M. J., & Xie, Y. (2011). MorphCache: A reconfigurable adaptive multi-level cache hierarchy. In Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011 (pp. 231-242). [5749732] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2011.5749732