Multi-level on-chip memory hierarchy design for embedded chip multiprocessors

Ozcan Ozturk, Mahmut Kandemir, Mary Jane Irwin, Suleyman Tosun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

This paper proposes an integer linear programming (ILP) solution to the combined problem of memory hierarchy design and data allocation in the context of embedded chip multiprocessors. The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining optimal on-chip memory partitioning across processors and data allocations across the resulting memory components. Our experimental results show that the applicationspecific on-chip memory hierarchies designed using this approach are much more energy efficient than conventional (pure shared or pure private) on-chip memories, conventional caches, and those designed by a prior work that partitions memory space across parallel processors without designing a multi-level hierarchy.

Original languageEnglish (US)
Title of host publicationProceedings - 12th International Conference on Parallel and Distributed Systems, ICPADS 2006
PublisherIEEE Computer Society
Pages8-15
Number of pages8
ISBN (Print)0769526128, 9780769526126
DOIs
StatePublished - 2006
Event12th International Conference on Parallel and Distributed Systems, ICPADS 2006 - Minneapolis, MN, United States
Duration: Jul 12 2006Jul 15 2006

Publication series

NameProceedings of the International Conference on Parallel and Distributed Systems - ICPADS
Volume1
ISSN (Print)1521-9097

Other

Other12th International Conference on Parallel and Distributed Systems, ICPADS 2006
CountryUnited States
CityMinneapolis, MN
Period7/12/067/15/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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