MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.

S. C. Bass, B. J. Leon, W. K. Jenkins

    Research output: Contribution to conferencePaperpeer-review

    Abstract

    Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed.

    Original languageEnglish (US)
    Pages116-121
    Number of pages6
    DOIs
    StatePublished - 1974
    EventIEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974 - Phoenix, AZ, USA
    Duration: Nov 20 1974Nov 22 1974

    Other

    OtherIEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974
    CityPhoenix, AZ, USA
    Period11/20/7411/22/74

    All Science Journal Classification (ASJC) codes

    • Engineering(all)

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