Traditionally, the design of on-chip interconnects has been an afterthought in the design process of integrated circuits. As the complexity of interconnect and the capacitance, inductance and resistance associated with the wires have increased with technology scaling, the delays associated with wires can no longer be neglected. Consequently, planning the design of these interconnection networks early in the design stage has become critical in ensuring the desired operation of the integrated circuits. Network on Chip is an on-chip communication mechanism based on packet based data transmission to support early planning of interconnect design. This chapter reviews the various aspects of Network on a Chip and concludes with a case study of a neural network design using such a communication fabric.