Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

Theocharis Theocharides, Gregory M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingChapter

5 Scopus citations

Abstract

Traditionally, the design of on-chip interconnects has been an afterthought in the design process of integrated circuits. As the complexity of interconnect and the capacitance, inductance and resistance associated with the wires have increased with technology scaling, the delays associated with wires can no longer be neglected. Consequently, planning the design of these interconnection networks early in the design stage has become critical in ensuring the desired operation of the integrated circuits. Network on Chip is an on-chip communication mechanism based on packet based data transmission to support early planning of interconnect design. This chapter reviews the various aspects of Network on a Chip and concludes with a case study of a neural network design using such a communication fabric.

Original languageEnglish (US)
Title of host publicationAdvances in Computers
EditorsAli Hurson
Pages35-89
Number of pages55
DOIs
StatePublished - Dec 1 2005

Publication series

NameAdvances in Computers
Volume63
ISSN (Print)0065-2458

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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