New methodology for monitoring and comparing edge exposure and plasma charging current damage from plasma processing

S. J. Fonash, M. Ozaita, M. Okandan, O. O. Awadelkarim, Y. D. Chan

Research output: Contribution to conferencePaperpeer-review

Abstract

It is recently demonstrated that gate-definition reactive ion etching of polycrystalline silicon (poly-Si) gate, 0.5 μm channel length MOSFET transistors can cause plasma exposure edge damage in addition to the well-known plasma charging current damage. Here this paper focuses more closely on this gate edge damage and shows for the first time, that it manifests itself as distinct trapping and detrapping localized states at or near the SiO2/substrate Si interface in the thin gate oxide around the gate perimeter.

Original languageEnglish (US)
Pages84-86
Number of pages3
StatePublished - 1996
EventProceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID - Santa Clara, CA, USA
Duration: May 13 1996May 14 1996

Other

OtherProceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID
CitySanta Clara, CA, USA
Period5/13/965/14/96

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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