Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors

Sandeep Krishna Thirumala, Arnab Raha, Vijaykrishnan Narayanan, Vijay Raghunathan, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents an overview of the operation and applications of reconfigurable ferroelectric transistors (R-FEFETs) which offer unique logic-memory coupling in the device characteristics leading to novel circuit design possibilities. R-FEFETs feature dynamic reconfiguration between (a) volatile mode for logic operations and (b) nonvolatile mode for memory operation. An R-FEFET consists of two FE stacks which interact with each other and a common underlying transistor, to enable run-time tuning of hysteresis and the aforementioned reconfigurability. We discuss how such novel features of R-FEFETs can be utilized to design energy-efficient non-volatile memory (NVM) and non-volatile flip-flop (NVFF) designs. For NVMs, read-write conflicts can be effectively mitigated. In particular, R-FEFETs based 3T NVM exhibit significant advantage over existing standard FEFET based NVM design with 55% lower write power and 37-72% lower read power at iso-access time. R-FEFET based NVFFs offer the design options of an auto-backup (RNVFF-1) without the need of any additional circuitry/back-up control signals, or on-demand backup (RNVFF-2) with lower normal operational energy over RNVFF-1. Compared to an FEFET based NVFF, RNVFF-1 achieves 47% lower check-pointing energy, with a penalty of 6% in operation energy. RNVFF-2 shows 30% lower check-pointing energy with similar operation energy. At the system level, the RNVFFs achieve 25-33% register-level energy savings, in a state-of-the-art intermittently powered platform.

Original languageEnglish (US)
Title of host publicationNANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728155203
DOIs
StatePublished - Jul 2019
Event15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019 - Qingdao, China
Duration: Jul 17 2019Jul 19 2019

Publication series

NameNANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings

Conference

Conference15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019
CountryChina
CityQingdao
Period7/17/197/19/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering

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