TY - JOUR
T1 - Nonvolatile Processor Architectures
T2 - Efficient, Reliable Progress with Unstable Power
AU - Ma, Kaisheng
AU - Li, Xueqing
AU - Swaminathan, Karthik
AU - Zheng, Yang
AU - Li, Shuangchen
AU - Liu, Yongpan
AU - Xie, Yuan
AU - Sampson, John
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
This work was supported in part by the Center for Low Energy Systems Technology (LEAST); MARCO and DARPA; NSF awards 1160483 (ASSIST), 1205618, 1213052, 1461698, and 1500848; Shannon Lab Huawei Technologies; High-Tech Research and Development (863) Program under contract 2013AA01320; and the Importation and Development of High-Caliber Talents Project of Beijing Municipal Institutions under contract YETP0102. Xueqing Li and Vijaykrishnan Narayanan are the contact authors.
Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/1
Y1 - 2016/5/1
N2 - Nonvolatile processors (NVPs) have integrated nonvolatile memory to preserve task-intermediate on-chip state during power emergencies. NVPs hide data backup and restoration from the executing software to provide an execution mode that will always eventually complete the current task. NVPs are emerging as a promising solution for energy-harvesting scenarios, in which the available power supply is unstable and intermittent, because of their ability to ensure that even short periods of sufficient power, on the order of tens of instructions, will result in net forward progress. This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP. The authors propose a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses.
AB - Nonvolatile processors (NVPs) have integrated nonvolatile memory to preserve task-intermediate on-chip state during power emergencies. NVPs hide data backup and restoration from the executing software to provide an execution mode that will always eventually complete the current task. NVPs are emerging as a promising solution for energy-harvesting scenarios, in which the available power supply is unstable and intermittent, because of their ability to ensure that even short periods of sufficient power, on the order of tens of instructions, will result in net forward progress. This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP. The authors propose a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses.
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U2 - 10.1109/MM.2016.35
DO - 10.1109/MM.2016.35
M3 - Article
AN - SCOPUS:84976336478
SN - 0272-1732
VL - 36
SP - 72
EP - 83
JO - IEEE Micro
JF - IEEE Micro
IS - 3
M1 - 7478428
ER -