Numerical study of reduced contact resistance via nanoscale topography at metal/semiconductor interfaces

B. P. Downey, S. Datta, S. E. Mohney

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Reduction in contact size via scaling leads to an increase in parasitic contact resistance, which can be a limiting factor in aggressively scaled high-frequency transistors. Using numerical modelling, we predict that nanoscale topography at the metal/semiconductor interface can reduce the effective specific contact resistance by 25% or more using features 10 nm or less in width, even for doping densities as high as 1020 cm-3. Previous studies have shown that these features cause an increase in tunnelling current for lightly doped semiconductors. However, we have found that for heavy doping or low barrier heights, the main factor reducing contact resistance is increased interfacial area.

Original languageEnglish (US)
Article number015010
JournalSemiconductor Science and Technology
Volume25
Issue number1
DOIs
StatePublished - Feb 5 2010

Fingerprint

Contact resistance
contact resistance
Topography
topography
Metals
Semiconductor materials
Doping (additives)
metals
Transistors
transistors
scaling
causes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

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Numerical study of reduced contact resistance via nanoscale topography at metal/semiconductor interfaces. / Downey, B. P.; Datta, S.; Mohney, S. E.

In: Semiconductor Science and Technology, Vol. 25, No. 1, 015010, 05.02.2010.

Research output: Contribution to journalArticle

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